Current CPUs raise an exception when a hardware error or access violation occurs in executing a CPU instruction. If a CPU exception occurs, an interruption happens and exception handling code at a specified address is executed. When the exception handling is completed, processing returns to the location where the exception occurs and restarts the execution. For a critical error or special case, processing may not return to the location where the exception occurs.
There are various kinds of CPU exceptions, such as an error on execution, translation look-aside buffer (TLB) miss, and timer interruption. Their uses and conditions where an exception occurs are predefined, and the conditions cannot be flexibly changed in a software manner, i.e., cannot be programmably controlled. In other words, most exceptions do not intentionally occur in a location specified by a programmer.
A system call used for calling code of privileged mode from code of non-privileged mode and, for example, a trap instruction (tw instruction) of PowerPc (registered trademark of IBM) for determining by comparing two register values whether an exception is to be raised can raise the exception at a specified location. However, for the system call, the exception always occurs and cannot be disabled; for the above-described trap instruction, processing of acquiring two register values before execution and processing of comparing and determining the register values in the execution are necessary.
There is also a conditional branch instruction as a CPU instruction. A state that is a target for determination is reflected as a value of a register before a branch instruction is called, and whether branching is to be performed based on that value. A conditional branch instruction needs an operation on a volatile register in advance, and the conditional branch instruction itself is always executed even if branching is not performed.
In computer programming, special processing is often required to be performed only when a certain condition is satisfied. In such cases, a conditional branch instruction is typically used. That is, steps of updating a value of a register by some kind of operation in response to a CPU instruction and jumping to processing code in response to a conditional branch instruction depending on that value are performed. However, checking a rarely satisfied condition in a software manner each time is inefficient.
FIG. 1 illustrates a conditional branch instruction 10 for a condition that is rarely satisfied in the prior art. Suppose, for task A, initialization function init( ) is needed in very rare cases, i.e., only at the beginning and in calling func( ) after reset( ) and also init( ) is called only from the same process space as that for task B. Therefore, it is necessary to check whether the current state is a reset state before certain processing is started to perform initialization processing in the case of the reset state. If such a reset state rarely occurs, the time consumed in this checking process is wasted almost all the time. In particular, from the point of view of the assembler language level, which is shown at the right side, processing of determining whether the current state is a reset state in task B wastes time, for example, in the case of memory access occurring in some miner determination. Specifically, if an rst_f variable is a variable at an address indicated by a pointer variable of a structure member, i.e., if memory is frequently referred to, or if a conditional expression contains “and” or “or,” such as “if (A or B or C . . . ),” the consumed time is further longer.
Patent Literature 1 describes, in an exception handling control method for shifting processing to an exception handling procedure indicated by “CALL” or another instruction word, speeding up propagation to exception handling to enhance the speed of exception handling by scanning a list of exception handlers registered by exception handler registration means and shifting control of exception handling directly to an exception handler associated with an exception condition identifier.
Patent Literature 2 describes a microprocessor that can suppress consumption of a program memory required for a branch instruction by having, address setting means for setting an interruption address for each interruption cause in a region other than an instruction memory and a multiplexer for inputting an output of the address setting mechanism using a cause detected by an interrupt detecting circuit as a selection signal into a program counter, increase the efficiency of the program memory by deleting an inefficient space of the program memory, and shorten the time required for handling an interruption.
Patent Literature 3 describes an exception handling mechanism that can prevent the presence or absence of an exception handler from affecting a throughput of a normal processing program by preparing the normal processing program, a plurality of programs of exception handlers, and a previously coded execution state and exception status of the normal processing program at which it is necessary to select each of the exception handlers and perform exception handling, adding them as information in program code in association with respective exception handlers, comparing an execution state of the normal processing program occurring when an exception is detected with the information indicating the execution state of the normal processing program added for each exception handler, selecting an appropriate exception handler, and controlling the execution.